1. Field of the Invention
The present invention relates to a STI method for semiconductor processes, and more particularly, to a method of STI fabrication on a semiconductor wafer with superior gap filling ability, increased integration density and reduced junction leakage effects.
2. Description of the Prior Art
In semiconductor front-end processes, a shallow trench isolation (STI) technique is commonly used to provide sufficient isolation between electrical devices on a wafer. A typical STI process involves the formation of shallow trenches surrounding an active island, referred to as an xe2x80x9cactive areaxe2x80x9d, on the wafer. Then, an oxide layer or a liner is formed on the interior surface of the trenches by a thermal oxidation process followed by the filling in of the trenches with an insulating material to obtain electrical isolation effects. Due to an increased integration of the electrical devices fabricated on the wafer, the widths of the shallow trenches decrease leading to an increase in aspect ratio. The increase in the aspect ratio of trenches results in reduced gap filling ability and poor product reliability. Furthermore, the use of conventional thermal oxidation in the formation of a liner also hinders gap filling and increases junction leakage.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic cross-sectional diagrams of the fabrication of an isolating trench 14 on a semiconductor wafer 10 according to the prior art method. The figures are examples and not drawn to scale. As shown in FIG. 1, a patterned mask layer 25 with an opening 13 is first formed on a silicon substrate 12. The opening 13, formed by conventional lithography and etching processes, exposes a portion of the silicon substrate 12 and defines the location and pattern of a trench 14. Generally, the patterned mask layer 25 comprises a pad oxide layer 22, and a silicon nitride layer 24 laminated on the pad oxide layer 22. A conventional plasma dry etching process, such as a reactive ion etching (RIE), is then used to carve the silicon substrate not covered by the mask layer 25 to form a trench 14. The trench 14 has a depth H, a top width W1, and a bottom width W2. It is known that during the carving or etching of the silicon substrate 12, the silicon surface orientation gradually changes from a  less than 111 greater than  sidewall surface 16 to a  less than 100 greater than  bottom surface 18.
As shown in FIG. 2, due to damage of both the sidewall surface 16 and the bottom surface 18 during the RIE process, defects in the STI structure are produced. Thus, a thermal oxidation process, also known as a furnace oxidation process, is performed to oxidize the sidewall surface 16 and the bottom surface 18 at a temperature environment of 800xc2x0 C. to 1000xc2x0 C. to form a liner oxide layer 28 on the interior surface of the trench 14. Another objective of the thermal oxidation process is to round the corners of the sharp corner portions 19, located at the interface of the trench 14 and the horizontal surface of the silicon substrate 12, to release stress.
However, in a conventional thermal oxidation process, the growth rate, dielectric strength, interface trap density (Dit) and etc. of silicon oxide are strongly dependent on the surface orientation of silicon. Generally, the integrity of silicon oxide grown by thermal oxidation on the  less than 100 greater than  bottom surface 18 is poorer than on the  less than 111 greater than  sidewall surface 16. The difference in integrity leads to a significant decrease of the bottom width of the trench 14 from W2 to W3, as well as a significant change in aspect ratio, leading to a reduction in gap filling ability. For instance, in a conventional dry furnace oxidation, the silicon oxide thickness on the  less than 111 greater than  sidewall surface 16 is approximately 400 to 500 angstroms (xc3x85), while the silicon oxide thickness on the  less than 100 greater than  bottom surface 18 is normally less than 300 xc3x85. Also, in the conventional thermal oxidation process, the amount of corner-rounding of the corner portions 19 is not sufficient and results in high interface trap density in the conventional thermal liner oxide layer 28.
It is therefore a primary objective of the present invention to provide a method of fabricating an STI on a wafer with both superior gap filling and stress-releasing ability.
Another objective of the present invention is to provide a method of fabricating an STI on a wafer with superior gap filling ability, increased integration density and reduced junction leakage, by an oxidation process independent of Si surface orientation.
The present invention describes a method of fabricating an STI on a wafer using a plasma liner forming process that eliminates junction leakage commonly occurring in the prior art. The method begins by the formation of a patterned hard mask on a silicon substrate, preferably a P-doped single crystal silicon substrate. The patterned hard mask is a laminated layer comprising a pad oxide and a layer of silicon nitride and exposes a portion of the surface of the silicon substrate. The exposed portion of the silicon substrate is then dry etched to form a trench in the silicon substrate with both a  less than 100 greater than  surface and a  less than 111 greater than  surface. Next, a portion of the pad oxide is wet etched near the top corners of the trench to expose a portion of the top surface of the silicon substrate located beneath the silicon nitride layer surrounding the periphery of the trench. At a temperature of 400xc2x0 C., a microwave-excited high-density Kr/O2 plasma is induced to oxidize both the interior surface of the trench and the exposed top surface of the silicon substrate located beneath the silicon nitride layer surrounding the periphery of the trench beneath the layer of silicon nitride to form a silicon dioxide liner of uniform thickness on both the STI  less than 100 greater than  surface and the  less than 111 greater than  surface. The resulting conformal silicon dioxide liner displays superior corner-rounding effects and excellent integrity on both the  less than 100 greater than  surface and  less than 111 greater than  surface. Finally, an insulating material, such as HDP oxide, is deposited on the silicon substrate to fill in the trench followed by chemical-mechanical polishing.
In one preferred embodiment of the present invention, the thickness of the conformal silicon dioxide liner is less than 300 angstroms (xc3x85). The microwave-excited high-density Kr/O2 plasma is induced at a specific and enhanced electrical field strength. In an enhanced electrical field and microwave-excited high-density Kr/O2 plasma environment, the interior surfaces of the trench, i.e. the  less than 111 greater than  surface and  less than 100 greater than  surface, and the corner portions of the silicon substrate (STI edges) are synchronously oxidized to form a first oxide liner having a first predetermined thickness and a second oxide liner having a second predetermined thickness, greater than the first predetermined thickness, respectively.